Kingston Launches RAM for Intel Core i5 Platform
Thursday, September 24, 2009
Intel has made its new line of Core i5 CPUs official today and along with the new CPUs comes new RAM for machines using them. Kingston has announced that it is the first manufacturer to offer 2133MHz RAM for the Intel Core i5 platform. The RAM is for both the new i5 and the existing i7 Intel CPU lines. The HyperX RAM runs at 2133MHz and uses only 1.65 volts of power. 4GB dual channel kits are being offered and the kits have overhead for overclocking for additional performance. The RAM will be offered in 4GB 2133MHz CL8-8-8-24 for $394, 4GB 2133MHz CL9-9-9-27 for $269, 4GB 2000MHz CL8-8-8-24 for $198, 4GB 2000MHz CL9-9-9-27 for $140, 4GB 1600MHz CL9-9-9-27 for $137, 4GB 1600MHz CL9-9-9-24 at $132, and 4GB 1333MHz CL7-7-7-21 for $125.
Posted bySaini at 2:48 PM 0 comments
Labels: Memories
Rambus XDIMM
Friday, August 7, 2009
The Rambus XDIMM is a high capacity memory module designed with high performance XDR™ DRAM devices. It provides the upgrade flexibility, capacity, and performance essential for servers, consumer electronics, and main memory applications. Operating at up to 6.4Gbps data rates, a single XDIMM provides many times the bandwidth of today's module-based systems while enabling multi-gigabyte capacities. With Rambus Dynamic Point-to-Point technology, XDIMMs can be installed in single or dual configurations while maintaining full system bandwidth and preserving the signal integrity of a true point-to-point topology. The Rambus XDIMM is part of the XDR memory system solution, allowing system and chip designers to integrate the world's fastest memory technology while eliminating interoperability and signal integrity problems.
Posted bySaini at 6:06 AM 0 comments
Labels: Memories
Rambus XIO Controller IO Cell
Thursday, August 6, 2009
The XIO cell is the high-performance, low-latency controller interface to XDR™ DRAM memory devices. Using Octal Data Rate signaling at speeds of up to 7.2Gbps, the XIO IO cell can support bandwidths of up to 28.8GB/s from a single XDR DRAM device. The XIO can be configured to support multiple XDR devices thus providing the necessary memory bandwidth for demanding graphics, computing and consumer electronics applications. It can be used in tandem with the XMC memory controller or integrated with the customer’s logical controller design.
The XIO macro cell is composed of one or two 12-bit request bus blocks , one control block , and a variable number of 8-bit or 9-bit data blocks . The RQ block provides address and control information to the memory subsystem. The CTL block performs register access, initialization, maintenance and testability functions. Each DQ block is capable of transmitting and receiving data at up to 7.2Gbps data rates. FlexPhase™ circuits allow arbitrary per-pin DQ transmit and receive data phases eliminating the need for system trace length matching. The RQ block generates single-ended signals, while the DQ blocks transmit and receive ultra low-voltage Differential Rambus Signaling Level signals.
Posted bySaini at 10:44 PM 0 comments
Labels: Memories
Rambus' memory DDR3
Wednesday, July 22, 2009
Rambus' memory controller interface solution for industry-standard DDR3 DRAMs features a fully integrated macro cell which provides the physical layer (PHY) interface between the controller logic and DDR3 or DDR2 DRAM devices for data rates of up to 1600 MHz. Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer electronics, servers, and workstations. To serve these applications, Rambus has architected and developed a DDR3 memory controller interface macro-cell that engineers can seamlessly integrate into their customer owned tooling (COT) or application-specific integrated circuit (ASIC) timing adjustment circuits for precise on-chip data alignment with the clock
Calibrated output drivers.On-die software environment for bring-up, characterization and validation of the DDR3 interface in the end-user application.
Other key interface features include:-
800 to 1600 MHz data rates
Support for DDR3 and DDR2 signaling modes
On-chip phase-locked loop (PLL)
On-chip delay-locked loop (DLL)
Levelization support for fly-by command and address architecture
Variable data bit-widths (8-, 16-, 32-, and 64-bit) with optional ECC support
Rambus interface solutions provide a comprehensive architecture and system design, as well as design models and integration tools. Included in the solution are reference GDSII database, timing models, layout verification netlists, gate-level models, place-and-route outline, and placement guidelines. Package design and system board layout services are also available.
Posted bySaini at 3:10 PM 0 comments
Labels: Memories
Terabyte Bandwidth Initiative of Rambus
Wednesday, June 3, 2009
Famous Rambus Terabyte Bandwidth Initiative pioneers new memory signaling technologies useful for the development of a future memory architecture capable of delivering a terabyte per second of memory bandwidth to a single System-on-Chip. This unparalleled memory bandwidth will enable future memory systems to benefit from an order of magnitude improvement in 
memory performance.
To achieve 1 TByte/s memory bandwidth, Rambus has developed fundamental innovations that include:-
1. 32X Data Rate - A new memory signaling technology which transmits 32 data bits per input clock cycle;
2. Fully Differential Memory Architecture - Providing the benefits of differential signaling on both the DQ and C/A channels;
3. FlexLink™ C/A - The industry's first full speed, scalable, point-to-point command/address link.
With these innovations and others developed through the Terabyte Bandwidth Initiative, Rambus will provide the foundation for a future memory architecture that offers increased performance, higher and scalable data bandwidth, area optimization, and enhanced signal integrity for gaming, graphics and multi-core computing applications of the next decade.
Posted bySaini at 9:25 AM 0 comments
Labels: Memories
Rambus XDR memory
Tuesday, June 2, 2009
Famous Rambus XDR™ memory architecture is a total memory system solution that achieves an order of magnitude higher performance than today's standard memories while utilizing the fewest ICs. Perfect for compute and consumer electronics applications, a single, 4-byte-wide, 6.4Gbps XDR DRAM component provides 25.6GB/s of peak memory bandwidth. Key 
components enabling the breakthrough performance of the XDR memory architecture are:-
1. XDR DRAM is a high-speed memory IC that turbo-charges standard CMOS DRAM cores with a high-speed interface capable of 7.2Gbps data rates providing up to 28.8GB/s of bandwidth with a single device.
2. XIO controller IO cell provides the same high-speed signaling capability found on the DRAM, but adds additional enhancements like FlexPhase™ technology that eliminates the need for trace length matching.
3. XMC memory controller is a fully synthesizable logical memory controller that is optimized to take advantage of innovations like Dynamic Point-to-Point which provides for capacity expansion while delivering the signal integrity benefits of point-to-point signaling.
4. XCG clock generator provides the system clocks with four programmable outputs and is guaranteed to meet the clocking requirements for the XIO and XDR DRAM devices.
Posted bySaini at 4:09 PM 0 comments
Labels: Memories
Rambus XDR™2 Memory Architecture
Monday, June 1, 2009
The XDR™2 memory architecture is the world's fastest memory system solution capable of providing twice the peak bandwidth per device when compared to a GDDR5-based system. Further, the XDR2 memory architecture delivers this performance at 30% lower power than GDDR5 at equivalent bandwidth. Designed for scalability, power efficiency and manufacturability, the XDR2 architecture is a complete memory solution ideally suited for high-performance gaming, graphics and multi-core compute applications. Initial systems can achieve memory bandwidths of over 500GB/s into an SoC. Each XDR DRAM can deliver up to 38.4GB/s of peak bandwidth from a single, 4-byte-wide, 9.6Gbps XDR2 DRAM device, and the XDR2 architecture supports a roadmap to device bandwidths of over 50GB/s. Capable of data rates of 6.4 to 12.8Gbps, the XDR2 architecture is the latest generation in the award-winning family of XDR products. With backwards compatibility to XDR DRAM, the XDR2 architecture is part of a continuously compatible roadmap, offering a path for both performance upgrades and system cost reductions.
Posted bySaini at 3:07 PM 0 comments
Labels: Memories
